Intel® Core™ Architecture · Generation Eventide · 2028
EVENTIDE
Core Ultra 500 / Xeon 500 Series

The most architecturally ambitious APU Intel has ever built. Eventide doesn't iterate — it redefines the boundary between compute, graphics, AI, signal processing, and power at the process node level. A spiritual successor to Lunar Lake's efficiency ethos and Panther Lake's performance ambition, Eventide collapses six specialized silicon eras into a single, vertically integrated package.

Intel 04A · 0.4nm Intel 06E · 0.6nm Intel 14A-E FOveros 2.0 Photonic V8 HyperBOOST Arc Elementalist Xe5 256 TOPS NPU World-First AV2 Encode
COMPUTE INTEL 04A UHP · DP · SPE LOW POWER INTEL 06E UHE · LPE ARC E1080 ELEMENTALIST XE5 INTEL 04A ×4 TILES KACHE KORE™ L4 4GB bLLC LP iGPU ARC DRUID THREAD DIRECTOR HNPU 256 TOPS BIONZXR QS CORES DISPLAY 6 OUT IPU 8.2 2DKR LPNPU 88 TOPS KILLER X1 WiFi7 FOVEROS 2.0
Silicon Foundation
Four process nodes.
One package.

Eventide is the first consumer chip to leverage three distinct in-house Intel process nodes and a photonic tile interconnect simultaneously. Every tile is assigned its optimal manufacturing process — delivering performance, efficiency, and cost advantages that no monolithic design could achieve.

Intel 04A
Half-Nanometer Performance Node
The most advanced transistor node Intel has ever mass-produced
  • Process generation0.4nm-class GAA w/ GaNSi gate material
  • Transistor architectureGate-All-Around nanosheet, 4-stack
  • GaNSi advantageThermal conductivity 3× Si, near-zero tunnelling at sub-0.5nm
  • Interconnect metalRuthenium local interconnect, MoSi² contact
  • Power deliveryPowerVia 2.0 backside PDN + Hybrid Bonding
  • 3D stackingAdvanced Stacked Silicon Interconnect (ASSI) 2.0 — 0.4µm pitch hybrid bond
  • Voltage scaling0.35V min operating; sub-threshold Vt control ±2mV
  • Heat distributionGaNSi substrate lateral thermal spreading; peak 850 W/m·K
  • Tiles built on 04ACompute, Kache Kore™, iGPU (Arc E1080), HNPU
+62%
Perf/mm² vs 14A
−48%
Active power vs 14A
+38%
Max clock headroom
Intel 06E
Efficiency-First Node
Ground-up design for Performance Per Watt, not raw clocks
  • Process generation0.6nm-class FinFlex GAA, efficiency-biased Vt
  • Design philosophyIPC and PPW maximized; frequency ceiling deliberately soft-capped
  • Leakage controlUltra-low standby leakage: <0.3nA/µm gate leakage
  • Clock networkMulti-Vt adaptive body biasing; resonant clock mesh
  • Power deliveryPowerVia 1.5 backside PDN; granular per-cluster DVFS
  • Idle power stateClockgate + power gate in <1ns; sub-µW idle per cluster
  • IPC advantage+22% IPC uplift vs 14A at same frequency
  • Tiles built on 06ELow Power Island (UHE+LPE), LPiGPU (Arc Druid), QuickSync BionzXR, LPNPU
+54%
PPW vs Intel 14A
−61%
Idle leakage vs 14A
+22%
IPC vs 14A node
Intel 14A-E
Extended Mature Node
Battle-proven 14A for cost-optimal, reliable ancillary tiles
  • Process generation14A architecture, extended yield variant (14A-E)
  • RibbonFET generation3rd-gen RibbonFET with Backside Power Delivery
  • Extension differencesWider design rules for higher yield; SRAMs optimized for density
  • Cost roleMost cost-efficient node on package; reduces BOM on non-critical tiles
  • Tiles built on 14A-EMFX QuickSync, IPU 8.2, 2DKR, vPro/Pluton, Network I/O, SmartSound, Wake-on-Voice, Display partial logic
Mature
High-yield baseline
Min
BOM contribution
>98%
Tile yield rate
FOveros 2.0
FiberOptic-VEROS Photonic Interconnect
World-first photonic tile interconnect in a consumer package
  • Co-developed withLightmatter USA (photonic interconnect IP)
  • Interconnect mediumSilicon photonic waveguides; on-package optical mesh
  • Bandwidth (tile-to-tile)Up to 448 Tbps aggregate photonic bandwidth
  • Latency vs copper~70% lower tile-to-tile signaling latency vs Foveros 1.0 copper
  • Signal power~0.08 pJ/bit vs ~2.5 pJ/bit electrical at equivalent bandwidth
  • ModulationPAM-8 silicon photonic ring modulators; 1310nm wavelength
  • Electrical fallbackHybrid copper+photonic; copper used for low-latency control paths
  • GPU multi-tile syncEnables 4× E1080 tiles to present as single render device via hardware arbitration
448
Tbps photonic BW
−70%
Tile-to-tile latency
×31
Signal efficiency vs Cu
Photonic Tile Interconnect · Co-developed with Lightmatter USA
FOveros 2.0
Photonic
Lightmatter USA Silicon Photonic IP World-First Consumer PAM-8 · 1310nm

FOveros 2.0 — FiberOptic-VEROS — is the result of a deep engineering collaboration between Intel and Lightmatter USA, the photonic interconnect IP company. Every tile-to-tile data path inside Eventide runs on silicon photonic waveguides, not copper. Light replaces wire. The result: 448 Tbps of aggregate bandwidth at 0.08 pJ/bit — a 31× efficiency gain over equivalent electrical links. And because photons travel faster through the waveguide medium than electrons through copper at scale, tile-to-tile signaling latency drops by ~70%. This is what makes the 4× E1080 GPU multi-tile configuration possible — and what makes Kache Kore™ an effective bLLC for the entire SoC at once.

448
Tbps aggregate photonic bandwidth
−70%
Tile-to-tile latency vs Cu Foveros 1.0
×31
Signal efficiency vs copper at bandwidth
0.08
pJ/bit (vs ~2.5 pJ/bit electrical)
ON-PACKAGE PHOTONIC MESH — FOVEROS 2.0
COMPUTE
INTEL 04A · UHP+DP+SPE
⟺
KACHE KORE™
L4 4GB bLLC
ARC E1080
×4 TILES · XE5
⟺
LP ISLAND
INTEL 06E · UHE+LPE
HNPU + LPNPU
344 TOPS TOTAL
⟺
MEDIA + I/O
BIONZXR + IPU

PAM-8 ring modulators · 1310 nm wavelength
Copper hybrid fallback for low-latency control paths

4× E1080 MULTI-TILE UNIFICATION

FOveros 2.0 photonic arbitration + HW Thread Director allow four discrete Arc E1080 tiles to present as a single render device to drivers and games — unified command queues, unified framebuffer. Impossible with copper interconnects at this scale.

Core Architecture
Five core types.
One unified vision.

Eventide introduces the most segmented core architecture in x86 history — each core type purpose-built for a specific performance regime. Complexity is managed by the dedicated Thread Director tile and FOveros 2.0 photonic scheduling bus, not software.

— COMPUTE TILE · INTEL 04A —
Compute Tile · UHP Core
SOLAR ECLIPSE
Ultra High Performance · P-core Evolution

The UHP is Intel's fastest-clocking x86 core ever. Built wide for heat dispersion, it sacrifices peak IPC density in favor of raw frequency headroom. V8 HyperBOOST allows octets of UHP cores to fire in sequential bursts using a Ford Mustang V8 cylinder-offset firing pattern, sustaining effective 10 GHz workloads across thermally aware hardware scheduling windows. No SMT — threads are power, not sharing.

Base Clock
2.4 GHz
Max Turbo (TBM 5.0)
6.0 GHz
V8 HyperBOOST
10 GHz
Burst Duration
~8–40ms / cycle
SMT
None
Process
Intel 04A
Pipeline width
8-wide decode
L0 extra-LL cache
96 KB/core
L2 cache
4 MB/core
Octet burst grouping
8-core V8 firing
HW scheduler use
Pre-distributed
Core size
Large (thermal)
GEN-ON-GEN vs PANTHER LAKE P-CORE
Peak clock
+67%
IPC (ST)
+18%
ST Perf burst
+210%
Compute Tile · DP Core
SUNSET COVE
Dense Performance · SMT P-Core

The DP core is the IPC workhorse of Eventide — the highest IPC uplift of any core in this generation's lineup. It reintroduces Hyper-Threading to the P-core class (removed since Lion Cove) with a new 2-thread-per-core implementation featuring disjoint execution ports, minimizing thread contention. While it cannot match the UHP's raw clock ceiling, its instruction throughput per mm² is unmatched in the x86 landscape.

Base Clock
2.1 GHz
Max Turbo
5.2 GHz
SMT
2T / core (P-SMT)
Logical threads
2× core count
Pipeline width
10-wide decode
OOO ROB depth
720 entries
L0 extra-LL cache
128 KB/core
L2 cache
6 MB/core
Execution ports
20 (dual-thread aware)
Process
Intel 04A
V8 HyperBOOST
Not supported
IPC class
Highest on-chip
GEN-ON-GEN vs PANTHER LAKE P-CORE
IPC (ST)
+38%
MT throughput
+92%
Perf/W (MT)
+44%
Compute Tile · SPE Core
VENUSMONT
SPammable E-Core · Extreme Density

Nine SPE cores fit in the same die footprint as a single UHP core. Designed for massively parallel workloads traditionally requiring server infrastructure: scientific compute, AI data prep, parallel compilation, simulation. The X500 SKU can house hundreds of SPE cores across four compute tiles, delivering server-grade thread counts in a mobile chassis.

Core density
9× per UHP footprint
Base Clock
1.8 GHz
Max Turbo
3.6 GHz
SMT
None
Pipeline width
4-wide decode
L0 cache
24 KB/core shared
Shared L2
2 MB / 9-SPE cluster
Process
Intel 04A
Max in X500
288+ cores
Power state
Per-core fine gate
ISA extensions
AVX-512, VNNI2
Scheduling
HW Thread Director
GEN-ON-GEN vs PANTHER LAKE E-CORE
Core density
+320%
MT throughput
+280%
Perf/W
+38%
— LOW POWER ISLAND · INTEL 06E —
Low Power Island · UHE Core
LUNAR ECLIPSE
Ultra High Efficiency · Next-Gen Lunar Lake Heir

The UHE is the spiritual successor to the Lunar Lake efficiency core — but now manufactured on Intel 06E, a purpose-built efficiency node. The result is a core that meets or exceeds last-generation P-core performance while operating at dramatically lower voltages. As in Lunar Lake's philosophy, the system preferentially delegates all workloads to UHE cores before escalating to the Compute Tile. The Low Power Island can sustain all typical productivity, browsing, streaming, and communication tasks indefinitely with the Compute tile fully powered off.

Base Clock
1.6 GHz
Max Turbo
4.8 GHz
Performance target
≥ PTL P-core (ST)
TDP operating range
1.2W – 8W
SMT
None
L2 cache
3 MB/core
Shared with
Kache Kore™ L4
Process
Intel 06E
Pipeline width
6-wide decode
Idle power
<0.2W (gate off)
GEN-ON-GEN vs PANTHER LAKE LP-E CORE
ST perf
+52%
PPW (active)
+68%
Min operating W
−55%
Low Power Island · LPE Core
DARKMONT
Low Power Efficiency · Rebinned E-Core on 06E

Darkmont takes the last-generation E-core architecture from Panther Lake and rebins it onto Intel 06E, achieving a dramatic reduction in operating power. At slight undervolting, LPE cores operate in fractions of a watt — enabling a world-first scenario where the system draws as little as 1–5W total under active light use. Video playback, Zoom calls, web browsing, and background tasks are all within the LPE's sustained operational envelope without touching the UHE or Compute Tile.

Base Clock
0.8 GHz
Max Turbo
3.0 GHz
Min operating power
0.18W / core
System draw (LPE only)
1–5W active
SMT
None
Architecture base
PTL E-core, 06E rebin
L2 (shared cluster)
1 MB / 4-core cluster
Process
Intel 06E
Primary use case
BG tasks, video, calls
Undervolt certified
−80mV bin
GEN-ON-GEN vs PANTHER LAKE E-CORE
Min power/core
−72%
System idle W
−60%
IPC (same Vf)
+22%
Kache Kore™

4GB bLLC / L4 cache on Intel 04A. Central cache for all tiles. Acts as cache-latency DRAM for the APU — eliminates DRAM round-trips for hot working sets.

V8 HyperBOOST 1.0

Octets of UHP cores fire in Ford Mustang V8 offset sequence. Hardware Thread Director pre-schedules burst windows. Sustains effective 10 GHz throughput for frequency-bound tasks within thermal budget.

Turbo Boost Max 5.0

Next evolution of Intel's binning-based boost algorithm. Continuous per-core voltage-frequency profiling. Feeds V8 HyperBOOST with real-time thermal headroom data.

Thread Director Tile

Dedicated silicon scheduler tile. Handles 5-class core arbitration, tile sleep/wake, GPU escalation, NPU offload decisions, and thermal budget allocation — all in hardware, at sub-100ns latency.

Sonoral™

Intel's implementation of AcoustX: SoRT acoustic ray-tracing silicon stacked on the Klangkerne tile. Hardware BVH traversal, UTD diffraction and binaural rendering at 0.0% frame cost — 118mW for what costs a CPU 1.8W.

AcoustX

The open, royalty-free acoustic ray-tracing API (acx.dll / libacx.so). listener.h for native listener-out rendering; compat.h recompiles Steam-Audio-era titles at 94% lower power. Sonoral is the first conformant implementation.

Cache Architecture · Intel 04A
Kache Kore™
How Intel Beats x3D

AMD's 3D V-Cache stacks extra SRAM on top of the CPU die. Kache Kore™ is Intel's counter-strike — a dedicated 4 GB beyond-Last-Level Cache tile built on Intel 04A, directly connected to every tile on the SoC via FOveros 2.0 photonic short-path. It's not just more cache — it's cache at a scale that functions as cache-latency DRAM for the entire APU. The 4 GB bLLC holds entire game working sets, eliminating DRAM round-trips entirely for hot data. Where AMD's x3D tops out at 192 MB, Kache Kore™ delivers over 4,000 MB — and it's shared across CPU, GPU, and NPU simultaneously.

AMD 3D V-CACHE
3D V-Cache
  • · 64 MB or 96 MB stacked SRAM
  • · CPU-only benefit
  • · Does not help GPU workloads
  • · High cost: stacked silicon process
  • · Fixed allocation, no dynamic sharing
INTEL KACHE KORE™ bLLC
Kache Kore™
  • · 4 GB bLLC — 40× AMD V-Cache size
  • · CPU, GPU, NPU all benefit
  • · Shared across all APU tiles via photonics
  • · Intel 04A — cost-efficient at 0.4nm
  • · HW Thread Director dynamically routes hot data
4 GB
bLLC on Intel 04A
×40
vs AMD 3D V-Cache size
100%
APU-unified (CPU + GPU + NPU)
−70%
DRAM round-trips for hot worksets
GAMING IMPACT
  • 1% low frametime stabilityNear-eliminated stutter
  • Open world streamingFull zone held in bLLC
  • GPU framebuffer cachingbLLC reduces VRAM pressure
  • AI model inferenceModel weights cached in bLLC
Dedicated Scheduler Silicon · HW Thread Director
Thread Director
Unified Intelligence.

The Hardware Thread Director is not firmware. It is dedicated silicon — a purpose-built scheduling tile that operates independently of all CPU cores, making real-time arbitration decisions at sub-100ns latency. With Eventide's 5-class heterogeneous core architecture (UHP, DP, SPE, UHE, LPE) spanning two process nodes, software schedulers simply cannot respond fast enough. The Thread Director tile monitors every core's thermal headroom, instruction profile, and priority class simultaneously, and reassigns threads in hardware without OS intervention.

A new capability in Eventide: the HW Thread Director now operates in co-pilot mode with the LPNPU. The always-on Low Power NPU (88 TOPS, Intel 06E) runs a lightweight on-chip AI scheduling model that predicts workload class in advance — feeding predictive dispatch decisions to the Thread Director before threads even become runnable. The result: smarter core selection, fewer thermal missteps, and better sustained performance over time.

The Thread Director is also the enforcement engine behind System AFFINITY™ — Eventide's hardware power identities. The same physical chip glides at 0.5W on battery and, on high-end SKUs, scales to a 2,000W monster in its dock, with the Thread Director holding smoothness constant across the entire range.

Open Thread Director Technology Page →
  • 🎯
    5-Class Core Arbitration
    Real-time assignment across UHP, DP, SPE (04A) and UHE, LPE (06E) based on instruction class, priority, and thermal head
  • 🧠
    LPNPU Co-Pilot (AI-Assisted Scheduling)
    Always-on LPNPU runs predictive workload classification — pre-routes threads to optimal core class before scheduling window opens
  • ⚡
    V8 HyperBOOST Sequencer
    Pre-schedules UHP burst firing windows using TBM 5.0 thermal data — coordinates the 1-4-6-3-8-5-7-2 offset sequence
  • 💡
    Tile Sleep / Wake Orchestration
    Powers down entire compute tiles in microseconds. Wakes GPU, NPU, BionzXR tiles on-demand — below OS visibility
  • 🔀
    GPU Escalation + NPU Offload
    Identifies AI and graphics tasks in CPU instruction stream; offloads to HNPU or Arc E1080 without driver round-trip
THREAD CLASSIFICATION → CORE DISPATCH
LATENCY
→ UHP Solar Eclipse (04A)
THROUGHPUT
→ DP Sunset Cove (04A)
PARALLEL
→ SPE Venusmont (04A)
BALANCED
→ UHE Lunar Eclipse (06E)
BACKGROUND
→ LPE Darkmont (06E)
AI TASK
→ HNPU/LPNPU (silicon offload)
GRAPHICS
→ Arc E1080 / Druid
LPNPU CO-PILOT

The LPNPU (88 TOPS, <1.4W, always-on) runs Intel's on-chip workload prediction model. It classifies upcoming instruction patterns and feeds pre-routing signals to the Thread Director — allowing proactive core preparation before threads become runnable.

  • Scheduling latency<100ns hardware
  • Core classes managed5 (UHP, DP, SPE, UHE, LPE)
  • Process nodeIntel 14A-E (scheduler logic)
  • LPNPU AI assistYes — predictive dispatch
  • OS dependencyNone — fully hardware-native
UHP
SOLAR ECLIPSE
DP
SUNSET COVE
SPE
VENUSMONT
UHE
LUNAR ECLIPSE
LPE
DARKMONT
Thread Director Analytics · Architecture Efficiency
Core Architecture
Comparison.

Five core classes, five distinct power envelopes. These graphs illustrate how each architecture occupies its own region of the performance-efficiency curve — enabling the Thread Director to make optimal dispatch decisions based on workload characteristics and thermal budget.

PERFORMANCE PER WATT · ALL CORE CLASSES
0 0.25× 0.5× 0.75× 1.0× 0W 5W 10W 15W 20W ACTIVE POWER (WATTS) RELATIVE PERF LPE UHE SPE DP UHP LP ISLAND ZONE 10 GHz BURST
CLOCKS PER WATT · FREQUENCY vs POWER
0 2.5 5.0 7.5 10 0W 5W 10W 15W 20W ACTIVE POWER (WATTS) FREQUENCY (GHz) LPE UHE SPE DP UHP 10 GHz BURST
IPC PER WATT · INSTRUCTIONS PER CYCLE
0 2 4 6 8 0W 5W 10W 15W 20W ACTIVE POWER (WATTS) IPC LPE UHE SPE DP UHP 720-ENTRY ROB
Graphics Architecture · Eventide
Three GPU architectures.
One for everything.

Eventide houses three distinct graphics architectures: Arc Elementalist for extreme performance, Arc Druid for sustained efficiency, and the 2D Kanvas Renderer for zero-cost desktop composition. Each operates on dedicated silicon — freeing every transistor to do exactly what it was designed for.

Elementalist
Xe5 Architecture · Intel 04A · Performance iGPU

The fifth-generation Xe architecture — the widest shader core, deepest wave dispatch, and first native-FP64 execution unit Intel has ever shipped. XMX5 matrix acceleration with sub-byte INT2/FP4 precision. RTU5 ray tracing with BVH4 traversal and VR stereo BVH caching. Up to four tiles fused via FOveros 2.0 photonic fabric into one GPU — the first iGPU to decisively surpass dedicated desktop flagships.

  • Shader generationXe5 · 5th-gen unified shader · 2.2× IPC over Xe2
  • AI computeXMX5 · INT2 / FP4 / INT8 / FP8 / BF16 native
  • Ray tracingRTU5 · BVH4 · ReSTIR · VR stereo BVH
  • ProcessIntel 04A · FOveros 2.0 photonic · up to ×4 tiles
  • Featured GPUArc E1080 · see GPU Lineup section ↓
vs XE2 (BATTLEMAGE)
Shader IPC
+120%
AI TOPS/unit
+340%
RT rays/clock
+200%
Druid
Xe4E Architecture · Intel 06E · Efficiency LP iGPU

A purpose-built efficiency variant of the Xe4 desktop architecture, re-fabbed on Intel 06E. Per-shader power gating — each EU powers off completely when idle, not just clock-gated. Adaptive clock stepping adjusts voltage-frequency per-core every 100μs. XMX4E GPU matrix acceleration for high-throughput Windows AI workloads. Hardware RTU4 ray tracing at LP TDPs. 3W sustained active floor.

  • Shader generationXe4E · per-shader power gating · 3W floor
  • AI computeXMX4E · GPU-coupled · ~553 TOPS (D390)
  • Ray tracingRTU4 · hardware BVH · area-light sampling
  • ProcessIntel 06E · −35% power/transistor vs 04A
  • Featured GPUArc D390 · see GPU Lineup section ↓
vs PANTHER LAKE iGPU
Perf-per-watt
+58%
AI TOPS (always-on)
+280%
Active power floor
−62%
2D Kanvas Renderer
2DKR · Intel 14A-E · Dedicated 2D Silicon

Purpose-built silicon for all desktop GUI composition. Zero 3D ALUs. Zero shaders. Zero Z-buffers. The 2DKR handles every pixel you see when you're not gaming — windows, taskbar, overlays, scrolling — at sub-millisecond latency and under a watt. During gaming, it renders all 2D overlays with zero GPU overhead, freeing the Arc Elementalist and Druid entirely for 3D workloads.

  • ArchitectureModernised Blitter Engine · scanline pipeline
  • 3D capabilityNone — pure 2D acceleration
  • Power<1W active · <0.1W idle · 0W GPU overhead
  • ProcessIntel 14A-E · ~4 mm²
  • RoleDesktop composition · game overlays · API routing
vs GPU-BASED DESKTOP COMPOSITION
Desktop idle W
−85%
UI frame latency
−92%
GPU freed for 3D
100%
AI Rendering Technology · Powered by HNPU + Xe5
XeSS 5.0
NEXT IN AI RENDERING

Eventide's Xe5 architecture and 256-TOPS HNPU combine to deliver Intel's most advanced AI rendering suite yet — XeSS 5.0 upscaling, XeFG 3.0 frame generation, Xe-MFG 2.0 multi-frame generation, and the new XeLL Pro+ latency compensation system. Together they transform raw GPU performance into the highest-quality, lowest-latency gaming experience on any mobile platform.

HNPU-Accelerated Xe5 Architecture 4× Frame Multiplier
XeSS 5.0 · AI UPSCALING
XeSS 5.0
Xe Super Sampling — 5th Generation

5th-gen AI upscaler powered by HNPU XMX5. Near-native image quality at Performance preset. Temporal stability improvements rival native rendering in motion clarity and fine detail.

Quality modeNear-native IQ
Perf upliftUp to 3.5× framerate
AccelerationHNPU XMX5 units
SDKOpenXeSS 5.0 API
XeFG 3.0 · FRAME GENERATION
XeFG 3.0
Xe Frame Generation — 3rd Generation

AI frame interpolation generating synthetic frames between rendered frames. 3rd-gen model improves motion handling and ghosting elimination by 60% vs XeFG 2.0.

MultiplierUp to 2× per frame
w/ XeSS combinedUp to 7× effective fps
Motion quality+60% vs XeFG 2.0
APIDX12 / Vulkan
Xe-MFG 2.0 · MULTI-FRAME
Xe-MFG 2.0
Xe Multi-Frame Generation — 2nd Generation

Generates multiple AI frames per single rendered output. Combined with XeSS 5.0, achieves up to 4× frame multiplication — the most aggressive frame gen Intel has shipped.

Max multiplier4× (with XeSS 5.0)
AI engineHNPU + Xe5 XMX5
Min native fps30 fps for quality
Frames generated2–4 per render
XeLL Pro+ · LATENCY
XeLL Pro+
Xe Low Latency Pro+

Anti-latency system with hardware frame warp. Reads mouse and controller input at the hardware level, shifts the completed frame in the direction of motion before it reaches the display, then runs an HNPU edge-regeneration pass to AI-inpaint the newly revealed screen borders — eliminating the perceptual lag introduced by frame generation entirely.

Frame shiftInput-driven motion warp
Edge regenHNPU AI border inpainting
Effective latency≤ native w/ 4× MFG
Works withXeFG 3.0 + Xe-MFG 2.0
Arc GPU Family · Performance Tiers
The Arc 1000 Series.
A new tier is born.

Intel Arc is structured around performance tiers from everyday to extreme. The 1000 Series is the first tier to leave dedicated desktop flagships behind — in every metric.

300
Entry Level
Everyday computing, streaming, and light gaming for thin-and-light platforms.
500
Midrange
Capable 1440p gaming and strong AI assist for mainstream performance laptops.
700
High End
4K gaming and ray tracing headroom. Near-dedicated GPU performance for premium content creation.
1000
Elementalist · Xe5 · Enthusiast
The first Arc tier to decisively surpass dedicated desktop flagships. Xe5 shader architecture, XMX5 matrix acceleration, and RTU5 ray tracing on Intel 04A — the world's most advanced mobile node. Up to ×4 FOveros tiles, unified as a single render device.
Xe5 Architecture XMX5 AI RTU5 Ray Tracing Intel 04A
Arc 1000 Series · GPU Lineup
Choose your
performance tier.

E-series carries Elementalist Xe5 from the flagship ×4-tile E1080 down to the budget E310. D-series carries Druid Xe4E for thermally-constrained LP mobile platforms.

E1080
Elementalist · Xe5 · Intel 04A · Up to ×4 Tiles

Purpose-built for multi-tile iGPU. A single E1080 tile delivers ~5× the raster performance of the RTX 5090 desktop. Four tiles on the X500 via FOveros 2.0 deliver ~20× RTX 5090 raster performance and ~67,830 combined AI TOPS.

  • Xe5-cores (per tile)220 · 112,640 shaders
  • XMX5 AI units (per tile)1,760 units · ~16,958 TOPS/tile
  • XMX5 combined (×4 tiles)7,040 units · ~67,830 TOPS
  • RTU5 (per tile)880 units
  • ROPs (per tile)320
  • TMUs (per tile)880 · 4 per Xe5-core
  • Pixel fill rate800 GPix/s/tile · 3.2 TPix/s ×4
  • Texture fill rate2,200 GT/s/tile · 8.8 TT/s ×4
  • GPU boost clock2.5 GHz
  • Max tile config (X500)×4 · single render device
  • MemoryKache Kore™ L4 (4 GB bLLC) + ZAM (FOveros-mounted)
  • VR supportVRV1 / VRV2 · stereo BVH caching
  • APIDirectX 13, Vulkan 1.4, OpenCL 3.1
PERFORMANCE vs COMPETITION — ×4 TILE
AI TOPS (×4 tiles)
RTX 5090
PRO 6000
Arc E1080
Raster single tile vs RTX 5090
RTX 5090
Arc E1080
D390
Druid · Xe4E · Intel 06E · LP Mobile

The flagship Druid efficiency GPU. RTX 5060M-class raster at 22W peak. Always-on in Eventide — handling sub-threshold GPU tasks without waking Elementalist tiles, keeping the system responsive at near-zero power cost.

  • Xe4E-cores14 · 3,584 shaders
  • XMX4E AI units112 units · ~553 TOPS
  • RTU4 ray trace units56 units
  • GPU boost clock2.4 GHz
  • TDP range3W – 22W (adaptive)
  • Target performanceRTX 5060M equivalent
  • PPW vs B390+58% performance-per-watt
  • Power statesStandby · low-activity · full (no shutdown)
  • APIDirectX 13, Vulkan 1.4, OpenCL 3.1
GEN-ON-GEN vs PANTHER LAKE ARC B390
Raster vs RTX 5060M
RTX 5060M
B390
Arc D390
Performance-per-watt
B390
Arc D390
Arc E-Series · Elementalist Xe5 · Extended Lineup
E770
Elementalist · Xe5 · rivals RTX 5090
Xe5-cores48
Shaders24,576
XMX5 units384 · ~3,700 TOPS
RTU5 units192
ROPs70
TMUs192
Pixel fill231 GPix/s
Texture fill634 GT/s
Boost clock3.3 GHz
ProcessIntel 04A
E750
Elementalist · Xe5 · RTX 5080 tier
Xe5-cores22
Shaders11,264
XMX5 units176 · ~1,696 TOPS
RTU5 units88
ROPs32
TMUs88
Pixel fill102 GPix/s
Texture fill282 GT/s
Boost clock3.2 GHz
ProcessIntel 04A
E580
Elementalist · Xe5 · RTX 5070Ti tier
Xe5-cores18
Shaders9,216
XMX5 units144 · ~1,387 TOPS
RTU5 units72
ROPs26
TMUs72
Pixel fill81 GPix/s
Texture fill223 GT/s
Boost clock3.1 GHz
ProcessIntel 04A
E560
Elementalist · Xe5 · RTX 5070 tier
Xe5-cores12
Shaders6,144
XMX5 units96 · ~925 TOPS
RTU5 units48
ROPs18
TMUs48
Pixel fill54 GPix/s
Texture fill144 GT/s
Boost clock3.0 GHz
ProcessIntel 04A
E390
Elementalist · Xe5 · RTX 5060Ti tier
Xe5-cores10
Shaders5,120
XMX5 units80 · ~771 TOPS
RTU5 units40
ROPs14
TMUs40
Pixel fill41 GPix/s
Texture fill116 GT/s
Boost clock2.9 GHz
ProcessIntel 04A
E380
Elementalist · Xe5 · RTX 5060 tier
Xe5-cores8
Shaders4,096
XMX5 units64 · ~617 TOPS
RTU5 units32
ROPs12
TMUs32
Pixel fill34 GPix/s
Texture fill90 GT/s
Boost clock2.8 GHz
ProcessIntel 04A
E310
Elementalist · Xe5 · RTX 5050 tier
Xe5-cores6
Shaders3,072
XMX5 units48 · ~462 TOPS
RTU5 units24
ROPs8
TMUs24
Pixel fill22 GPix/s
Texture fill65 GT/s
Boost clock2.7 GHz
ProcessIntel 04A
Arc D-Series · Druid Xe4E · Eventide LP Mobile Lineup
D380
Druid · Xe4E · RTX 5050M tier
Xe4E-cores10
Shaders2,560
XMX4E units80 · ~395 TOPS
RTU4 units40
TDP2W – 15W
ProcessIntel 06E
D310
Druid · Xe4E · Budget Mobile
Xe4E-cores6
Shaders1,536
XMX4E units48 · ~237 TOPS
RTU4 units24
TDP1W – 8W
ProcessIntel 06E
Platform Architecture · Tile Mosaic
Every function.
Its own silicon.

Eventide is not a monolithic processor. It is an orchestrated mosaic of purpose-built tiles — each manufactured on the process node optimal for its function, each operating independently or in concert. From always-on neural inference to 16K display output to zero-latency audio — this is what it means to build a complete platform from the silicon up.

Intel 04A · 06E · 14A-E FOveros 2.0 Photonic Fabric 12 Discrete Tile Domains Multi-Collab Engineering
◆   AI Compute Tiles
High-Performance NPU · Intel 04A
HNPU
Neural Processing Unit · Intel 04A · Compute Tile

The flagship neural processor in the Eventide lineup. Built on Intel's most advanced node, the HNPU delivers 256 TOPS with full INT2 through FP32 precision coverage and 32 MB of tightly-coupled on-die scratchpad SRAM for model weight staging. Handles Copilot+ AI features, real-time XeSS 5.0, LLM inference, and heavy background AI workloads — coordinated with the LPNPU by the Hardware Thread Director.

  • AI Throughput256 TOPS
  • Precision ModesINT2/4/8, FP8, BF16, FP16, FP32
  • On-die SRAM32 MB scratchpad
  • FrameworksOpenVINO 5.0, ONNX, TFLite, PyTorch
  • ProcessIntel 04A
256
TOPS
32
MB SRAM
7
Precisions
Low-Power NPU · Intel 06E
LPNPU
Always-On Neural Processor · Intel 06E · LP Island

Eventide's always-on intelligence layer. Running at under 1.4W peak, the LPNPU never sleeps — monitoring ambient audio for wake-on-voice, co-piloting the Hardware Thread Director with predictive AI task dispatch, and running SONAR presence detection from WiFi signal analysis. Combined system TOPS reach 344 across both NPUs.

  • AI Throughput88 TOPS
  • Peak Power Draw< 1.4W at full TOPS
  • Precision ModesINT4, INT8, FP8, BF16
  • Key RolesWake-on-Voice · SONAR · TD Co-Pilot
  • ProcessIntel 06E
ALWAYS-ON344 TOPS COMBINED
◆   Media & Codec Tiles
High-Performance Media · Intel × Sony · 06E
QuickSync BionzXR
8-Core Camera-Grade Transcoder · Intel 06E · Co-developed with Sony Semiconductor

The world's first camera-grade media engine integrated in a consumer mobile processor. Co-engineered between Intel QuickSync and Sony Semiconductor's BionzXR imaging silicon teams — the same BIONZ lineage found in Sony's α-series and Cinema Line cameras — the BionzXR Cores bring broadcast-grade transcoding directly to the APU package.

Delivers world-first AV2 hardware encode, full ProRes hardware encode at 8K120, AV1 decode at 8K240, and native VRV1/VRV2 for VR video pipelines. Sony USB-C/Thunderbolt plug-and-play: connect an α-series camera and immediately stream or encode RAW frames with zero software overhead.

  • Cores (X500)8× BionzXR cores
  • World-FirstAV2 hardware encode
  • Encode Peak8K120 ProRes · 8K240 AV1
  • Encode CodecsAV2, AV1, H.266/VVC, H.265, H.264, VP9, ProRes, VRV1, VRV2
  • Decode CodecsAll encode + VP8, MPEG-4, VC-1
  • Camera IntegrationSony USB-C / TB5 plug-and-play RAW ISP
  • ProcessIntel 06E
INTEL × SONY SEMICONDUCTOR BIONZXR LINEAGE CAMERA-GRADE
LP Media Engine · Intel 14A-E
MFX QuickSync
Low-Power Decode Engine · Intel 14A-E · LP Island

Always-on low-power decode for streaming, playback, and background media tasks. Offloads BionzXR from routine decode work, freeing the full codec engine for encode and capture pipelines. Runs the entire video decode stack at up to 35% lower power than the previous-generation QuickSync on Panther Lake.

  • Decode CodecsAV2, AV1, H.266/VVC, H.265, H.264, VP9, VP8
  • Encode (limited)H.265, AV1, H.264
  • Power Uplift−35% vs PTL QuickSync
  • ProcessIntel 14A-E
◆   Vision & Imaging
Image Processing Unit · Intel × Sony · 14A-E
Intel IPU 8.2
201MP Camera Pipeline · Intel 14A-E · Sony Native Integration

Eventide's Image Processing Unit supports up to 201 megapixel camera input, with Sony α-series and Cinema Line plug-and-play via USB-C and Thunderbolt 5. The ISP pipeline includes RAW demosaic, multi-frame HDR tone mapping, multi-band noise reduction, and lens distortion correction — all with LPNPU co-processing for real-time scene classification and computational photography.

  • Max InputUp to 201 MP
  • Camera IntegrationSony USB-C / TB5 native
  • ISP PipelineRAW demosaic · HDR · NR · Lens correction
  • AI Co-processingLPNPU real-time scene AI
  • ProcessIntel 14A-E
INTEL × SONY SEMICONDUCTOR α-SERIES NATIVE
◆   Audio
Audio Engine · Intel × Bang & Olufsen · 14A-E
Klangkerne™
Intel® Klangkerne™ Audio Engine · Intel 14A-E · Co-developed with Bang & Olufsen

The first fully vertically integrated audio stack on a consumer APU. Where every prior PC audio solution stacked Intel silicon → Realtek codec → WinAPI/DirectSound with multiplying latency at each handoff, the Klangkerne collapses that chain to a single in-package tile, co-engineered with Bang & Olufsen's acoustic DSP and tuning teams.

Built on Intel 14A-E, the Klangkerne implements the Intel × B&O Sound API — a purpose-built audio runtime exposing hardware-direct pathways to the Eventide OS, with WinAPI and DirectSound compatibility headers for Windows installations. Supports Dolby Atmos, DTS:X, B&O Beosonic spatial sound tuning, and multi-zone audio routing.

  • ArchitectureVertically integrated — no external codec
  • ProcessIntel 14A-E
  • Spatial AudioDolby Atmos · DTS:X · B&O Beosonic
  • Driver StackIntel × B&O Sound API (native OS)
  • Compat. HeadersWinAPI · DirectSound (Windows mode)
  • Key Design GoalsLatency · Efficiency · Sound Excellence
INTEL × BANG & OLUFSEN BEOSONIC TUNING DOLBY ATMOS DTS:X
GNA 5.0 · Audio AI Path
GNA 5.0
Gaussian & Neural Accelerator · Intel 14A-E

The Klangkerne works in tight coupling with the GNA 5.0 to deliver a completely hardware-offloaded audio intelligence pipeline. GNA handles always-on speech recognition, acoustic noise suppression, speaker identification, and wake-word detection — all at sub-milliwatt power, with results fed directly to the Klangkerne for immediate audio response without CPU involvement.

  • Always-On TasksSpeech · Noise · Wake-Word · Speaker ID
  • CouplingDirect hardware path to Klangkerne
  • CPU OverheadZero — fully offloaded
  • ProcessIntel 14A-E
◆   Display Engine
Unified Display Controller · 14A-E
Eventide Display Engine
Unified Multi-GPU Display Controller · Intel 14A-E · No MUX Required

The Eventide Display Engine unifies all display output from every GPU tier — Elementalist, Druid, and 2DKR — through a single centralised controller tile. No GPU-to-GPU frame copies, no MUX switch, no awkward GPU ownership per display. Any GPU handles any display simultaneously: Wallpaper Engine on LPiGPU, desktop UI on 2DKR, and a game on HPiGPU — all concurrently, with zero contention.

The flagship output interface is iDP 1.0 (Intel Display Protocol, an in-house eDP derivative over PCIe 6.0 ×16×3), capable of 16K at 1200Hz on a single cable — the backbone of the Sony XCDLED display ecosystem. Codec signal transport (VRV1/VRV2) allows resolutions that would exceed PCIe 6.0 ×16×3 raw bandwidth to be carried compressed without quality loss.

  • ArchitectureUnified — no MUX, no GPU-GPU copy
  • iDP 1.0Up to 16K@1200Hz · PCIe 6.0 ×16×3
  • iDP Color DepthUp to 96-bit (RGB+MCY)
  • DisplayPortDP 2.1b UHBR20
  • eDPeDP 1.6
  • HDMIHDMI 2.2
  • Max Displays6 simultaneous native
  • iDP CountUp to 2× iDP ports
  • VRRFull VRR · XCD-LED DIAC · HDR10+ Ultra · Dolby Vision 2
  • Codec TransportVRV1 / VRV2 over iDP for >raw bandwidth resolutions
  • ProcessIntel 14A-E
16K
iDP Max Res
1200
Hz (iDP)
6
Simultaneous Displays
96
Bit Color (iDP)
◆   Memory Subsystem
Memory Controller Tile · Lightmatter × Intel · FOveros-Mounted
ZAM Memory Controller
Zettascale Attached Memory Controllers · FOveros 2.0 Photonic Interconnect · Intel × Lightmatter

Eventide's memory subsystem is built around Lightmatter's photonic fabric and Intel's ZAM (Zettascale Attached Memory) architecture — a near-memory solution combining compute logic with DRAM stacks on the FOveros 2.0 base tile, delivering bandwidth fundamentally beyond conventional LPDDR or HBM solutions.

Base configurations ship with 2× dual-channel ZAM controllers for 5–6 TB/s effective bandwidth. Higher SKUs add a third DDR6/LPDDR6X dual-channel controller for capacity-prioritised workloads, bringing maximum unified memory to 2 TB. All tiles — CPU, GPU, NPU, audio, display — share this unified memory space via the photonic fabric, with the 4 GB Kache Kore™ bLLC acting as L4 cache to mask ZAM latency.

  • ZAM Controllers2× dual-channel (base) · 3× (higher SKU)
  • ZAM Bandwidth5–6 TB/s effective
  • ZAM Max CapacityUp to 1 TB ZAM
  • DDR6 ControllerDual-channel · DDR6-9600+ / LPDDR6X-10400
  • DDR6 Max CapacityUp to 1 TB DDR6
  • Max Unified MemoryUp to 2 TB (ZAM + DDR6)
  • bLLC (Kache Kore)4 GB L4 — masks ZAM latency
  • ECCYes — Xeon 500 class inline ECC
  • InterconnectLightmatter photonic FOveros 2.0 fabric
INTEL × LIGHTMATTER PHOTONIC FABRIC APU UNIFIED MEMORY
6
TB/s Bandwidth
2
TB Max Unified
4
GB bLLC Cache
ECC
Inline Error Correction
◆   Connectivity Tiles
Wireless · Intel × OPPO/BBK · 14A-E
Killer SignalBoost S1
Intel® Killer™ × OPPO SignalBoost S1 · Intel 14A-E · Up to 2× chips

The result of Intel Killer's gaming-intelligence stack meeting OPPO Semiconductor's signal engineering expertise. The S1 delivers quad-band WiFi 7 per chip, with dual-chip configurations giving Eventide X500-class systems eight simultaneous frequency bands, 360° Intel LinkBoost antenna coverage, and an integrated 5G modem.

The OPPO-derived AI LinkBoost and the Intel Killer Prioritization Engine work in tandem: hardware-level gaming traffic prioritisation combined with dynamic multi-band signal optimisation — maintaining consistent <30ms gaming latency even under maximum network contention.

  • WiFi StandardWiFi 7 (802.11be) · Quad-band per chip
  • Max Configuration2× S1 — 8 total bands
  • Max ThroughputUp to 11.5 Gbps combined
  • Cellular5G Sub-6 + mmWave · 4G LTE · VoLTE
  • BluetoothBluetooth Core 6.2
  • SONAR PresenceWiFi-signal proximity detection · LPNPU-powered
  • ProcessIntel 14A-E
INTEL KILLER OPPO SEMICONDUCTOR BBK ELECTRONICS
8
WiFi bands (2× chip)
7
WiFi Generation
360°
LinkBoost Antenna
Platform I/O Controller · Intel 14A-E
I/O Controller
Thunderbolt 6 · PCIe 6.0 · USB4 Gen 5 · NVMe 3.0 · 2.5GbE · Intel 14A-E

The centralised I/O tile governing all wired external connectivity. Houses the Thunderbolt 6 controller (160 Gbps symmetric), the PCIe 6.0 root complex, USB4 Gen 5 (80 Gbps), NVMe 3.0 storage interface, and Intel 2.5GbE Ethernet — all coordinated from a single tile on Intel 14A-E. Thunderbolt 6's Bandwidth Boost mode delivers up to 240 Gbps unidirectional for display-intensive workloads, and PCIe 6.0 ×4 feeds NVMe at up to ~24 GB/s sequential read.

The TB6 controller carries Intel Need Technologies — the platform's QoS arbitration framework that prioritises latency-critical tunnels (display, audio) over PCIe/USB bulk transfers when bandwidth is contested.

  • ThunderboltThunderbolt 6 · 160 Gbps sym · 240 Gbps boost
  • TB6 PortsUp to 4× TB6 / USB4 Gen 5 ports
  • PCIePCIe 6.0 root complex (storage / peripherals)
  • NVMeNVMe 3.0 · PCIe 6.0 ×4 · ~24 GB/s
  • USBUSB4 Gen 5 (80 Gbps) · USB 3.2 Gen 2×2
  • EthernetIntel 2.5GbE on-package
  • TB6 Compat.Backward compat. TB4, TB5, USB4, USB-C
  • ProcessIntel 14A-E
160
Gbps TB6 (sym)
240
Gbps TB6 Boost
24
GB/s NVMe
◆   Platform Security & Management
Platform Security & Management · Intel 14A-E
PSM Tile
Intel® CSME 2.0 · Silicon Security Engine · Intel® EGP · Microsoft Pluton · vPro® · Intel 14A-E

Eventide's Platform Security & Management tile consolidates all hardware-rooted security, management, and power control functions onto a dedicated 14A-E tile — isolating the security domain entirely from compute paths.

The tile implements Intel's Eventide Guardian Protocol (EGP), an in-house alternative to Microsoft Pluton providing a silicon root of trust with on-tile key management, attestation, and anti-rollback firmware validation — purpose-built for the Eventide OS security model. Pluton 2.1 is also included for Windows ecosystem compatibility. The CSME 2.0 provides out-of-band management (Intel AMT), hardware DRM, and secure boot chain, while the Silicon Security Engine handles on-tile certification authority and FW signing.

  • In-House SecurityEventide Guardian Protocol (EGP)
  • EGP FunctionsSilicon RoT · On-tile key vault · Anti-rollback · Attestation
  • Microsoft PlutonPluton 2.1 · Hardware TPM 2.1
  • Intel CSMECSME 2.0 · AMT · Hardware DRM · Secure Boot
  • SSESilicon Security Engine · On-tile CA · FW signing
  • Intel vPro®Yes — Xeon 500 class; HW-rooted vPro
  • DMA ProtectionIntel VT-d · DMA remapping · CET shadow stack
  • Threat DetectionIntel TDT AI · MITRE ATT&CK / ATLAS mapped
  • Power ManagementPlatform PUNIT · all-tile sleep/wake sequencing
  • ProcessIntel 14A-E
Unified Platform Fabric
All tiles. One fabric. Zero boundaries.

Every tile in the Eventide Tile Mosaic is interconnected by the Lightmatter photonic FOveros 2.0 fabric — providing coherent, low-latency access to the ZAM unified memory pool from CPU, GPU, NPU, audio, display, and I/O domains simultaneously. No discrete architecture compromises. Full deep-dives on each tile follow.

TILE COUNT
12
DISTINCT SILICON DOMAINS
Product Family
One generation.
Four tiers. Zero compromise.

Eventide is a unique one-off generation — not a platform. Each tier is purpose-engineered for a specific use profile, from the ultra-portable Core 500 to the no-limits Core Xeon 500.

Core 500
Essential / Mainstream
No Compute Tile
No High-Performance iGPU
Low Power Island (UHE + LPE)
LPiGPU (Arc Druid) only
LPNPU AI (88 TOPS)
2DKR, MFX QuickSync
HNPU (low config)
No BionzXR cores
Fanless designs; ultra-thin; extreme battery life.
Core i500
Mid to Enthusiast
Compute Tile (UHP + DP only)
No SPE cores
No Low Power Island
LPiGPU only (no E1080)
No NPU (AI disabled)
2DKR, MFX QuickSync, IPU
No BionzXR
F-suffix: no GPU at all
Classic Intel performance tier; gaming + workstation without LP complexity.
Core Ultra 500
High to Enthusiast / U500
Single Compute Tile
Limited SPE cores
Full Low Power Island
Up to ×1 Arc E1080
LPiGPU (Arc Druid)
HNPU 256 TOPS + LPNPU
BionzXR (up to 4 cores)
Full Affinity system
The everyday Eventide experience. Flagship laptop tier.
Core Xeon 500
X500 · Ultimate
Up to 4× Compute Tiles
288+ SPE cores
Full Low Power Island
Up to 4× Arc E1080
LPiGPU (Arc Druid)
HNPU 256 T + LPNPU 88T
8× BionzXR cores
Full Affinity + vPro + Pluton
No-compromise. Mobile supercomputer.
SKU Suffix Reference
U
Ultra-low power mobile
H
Mobile standard TDP
HX
Mobile with higher end GPU
HK
Unlocked mobile
HKX
Unlocked mobile with higher end GPU
F
No iGPU (i-SKU primarily)
V
Efficiency-specialised (LNL-style)
X
Higher end GPU
Product Family · Phone
One architecture.
Now in your pocket.

Intel Atom returns as Eventide's phone/mobile SoC tier — the same LP Island, Arc Druid and Thread Director architecture as Core 500, rescaled for a phone chassis. No Compute Tile, no Elementalist GPU, no Kache Kore — just 2DKR-first efficiency and, on Atom Ultra 500, a signature dual-Killer-S1 8-band WiFi bonding trick. Unlike the rest of Eventide, Atom bins by clock as well as core count: an 8-tier ladder running from the LPE-only Atom 500 A3 floor (2.6 GHz, no Lunar Eclipse cores at all) up to the Atom Ultra 500 P9 flagship (5.0 GHz) — with a dedicated 7-core config (P7, 2 UHE + 5 LPE) tuned for foldables along the way.

Atom 500
Mainstream Phone
No Compute Tile, no Elementalist GPU
0-2× Lunar Eclipse (UHE, 2.6-4.0 GHz) + 6-8× Darkmont (LPE)
A3: LPE-only floor SKU — no UHE cores at all
Compact LPiGPU (Arc Druid) + 2DKR compositor
LPNPU AI (88 TOPS, always-on)
No HNPU, no Kache Kore, no BionzXR
LPDDR6X primary memory (8-24 GB)
QuickSync MFX camera pipeline (2 cores, compact)
Single, compact Killer S1 (4 bands)
Everyday mainstream phones; extreme battery life.
Atom Ultra 500
Flagship Phone
No Compute Tile, no Elementalist GPU
2× Lunar Eclipse (UHE, 4.3-5.0 GHz) + 5-8× Darkmont (LPE)
P7: 7-core foldable config (2 UHE + 5 LPE)
Bigger LPiGPU (Arc Druid) class + 2DKR
LPNPU AI (88 TOPS, always-on)
No HNPU, no Kache Kore
LPDDR6X primary memory (12-28 GB)
Single BionzXR core (tiny) + QuickSync MFX
DX suffix: full-size dual Killer S1 (8 bands)
Signature dual-ISP WiFi bonding; the top phone tier.
Atom Suffix Reference
U
Ultra-low power (Atom 500)
UL
Ultra-low power, +RAM tier (Atom 500)
UXL
Ultra-low power, max RAM tier (Atom 500)
V
Efficiency-specialised (Atom 500)
VL
Efficiency-specialised, +RAM tier (Atom 500)
VXL
Efficiency-specialised, max RAM tier (Atom 500)
H
Standard TDP (Atom Ultra 500)
HL
Standard TDP, +RAM tier (Atom Ultra 500)
HXL
Standard TDP, max RAM tier (Atom Ultra 500)
DX
Flagship dual-ISP (Atom Ultra 500 only)
DXL
Flagship dual-ISP, +RAM tier (Atom Ultra 500 only)
DXXL
Flagship dual-ISP, max RAM tier (Atom Ultra 500 only)
HF
Foldable — 9-core 3+6 (Atom Ultra 9 only)
Intelligent Power Management
The AFFINITY™ System

Eventide's AFFINITY™ System is dynamic and user-choosable at the same time — the AI and the human share the wheel. Profiles are generated in real-time by the Hardware Thread Director working in tandem with the system AI (LPNPU co-pilot model); on NewGen's custom OS, users can pin, tailor, or hand-tune any profile and the HW-TD + LPNPU keep refining it at runtime. Enforcement happens in silicon — sub-millisecond transitions, wake vetoes, envelope caps.

AFFINITY is also context-aware: the machine carries a completely different profile set depending on whether it runs on battery, on a power adapter, or docked. And it is not a TDP throttle — profiles optimize for smoothness first, combining OS, hardware, and software tuning: 2D Kanvas keeps scrolling silky while GPUs sleep, FOveros 2.0 cuts power to entire tiles (dark fiber-optic interconnects leak nothing), the display drops below the industry 1Hz floor to true refresh-on-demand, and the OS itself stops ticking until the next event. Even the monstrous Core™ Xeon® 9 can AFFINITY down to 0.5–5W — then wake up in its dock as a 2,000W machine.

🔋 On Battery
0.5W – 45W envelope
Supersaver + Efficiency first; Balanced capped. LP Island leads, compute and GPU tiles power-cut.
🔌 On Adapter
15W – 175W envelope
Balanced and Performance unlock full turbo residency and sustained all-core work.
🧊 Docked
Up to 2,000W envelope
Specialized cooling + power-delivery dock: V8 HyperBOOST, all 4× E1080 tiles, All-Cores Unleashed — up to 2,000W on the top Core™ Xeon® 9.
SUPERSAVER
Battery · maximum quiescence
LPNPU + GNA managed
Active silicon
LPE cores only
All other tiles
Full power-cut
Display
0Hz refresh-on-demand
OS kernel
Fully tickless (event-driven)
2DKR
Sole display renderer
Typical TDP
0.5–5W
EFFICIENCY
Battery · casual daily use
LPNPU solo managed
Compute Tile
Full shutdown
UHE + LPE
Primary; background tasks
Arc E1080
Full shutdown
Arc Druid
Ultra-low standby
2DKR
Primary display renderer
Typical TDP
1–12W
BALANCED
Intelligent AI-driven arbitration
HW-TD + LPNPU managed
UHP cores
Boost on-demand only
V8 HyperBOOST
Disabled
Low Power Island
UHE primary; LPE overflow
Arc E1080
1 tile; others sleep
HNPU
Shared HNPU + LPNPU
Typical TDP
15–45W
PERFORMANCE
Max throughput · plugged in
HW-TD + LPNPU managed
UHP cores
All active; max turbo
V8 HyperBOOST
Off on battery; dock unlocks
DP + SPE
All active; full SMT
Arc E1080
1–2 tiles; scalable
HNPU
Full 256 TOPS
Typical TDP
55–95W
UNLEASHED
Docked · all cores · all GPUs
HW-TD + System AI profile
UHP cores
All active; V8 HyperBOOST
DP + SPE
All active; full SMT
Arc E1080
All 4 tiles; 20× RTX 5090
LP Island
Active (assist)
HNPU + LPNPU
Full 344 TOPS
Envelope
Up to 2,000W (X9 · dock)
⚡ COOLING + POWER-DELIVERY DOCK REQUIRED · TOP CORE™ XEON® 9 REACHES FULL 2,000W
Full AFFINITY™ + Thread Director Deep Dive →
SKU Selector
Eventide SKU Library

Filter Eventide SKUs by product family, series, suffix, and target price range. Select any SKU card to inspect a detailed summary, then open its full deep-dive specification sheet.

Series
Suffix
Price Range (USD)
$85to$10,999
Showing 0 SKUs
SKU Selector · Phone
Atom SKU Library

Filter Atom / Atom Ultra phone SKUs by series, suffix, and target price range. Select any SKU card to inspect a detailed summary, then open its full deep-dive specification sheet.

Series
Suffix
Price Range (USD)
$85to$500
Showing 0 SKUs
Intel, the Intel logo, Core, Core Ultra, Xeon, Arc, Thunderbolt, Killer, vPro, QuickSync, Thread Director, PowerVia, Foveros, and Turbo Boost are trademarks of Intel Corporation or its subsidiaries.
Sony, BionzXR are trademarks of Sony Group Corporation. Lightmatter FiberOptic integration is proprietary to the Intel-Lightmatter joint photonic development program.
Killer SignalBoost S1 developed in collaboration with OPPO Semiconductor Division and Intel Wireless Products Group.
Specifications subject to change. Performance numbers represent theoretical maximums under ideal conditions.
Eventide SKU Library · Intel Corporation 2028 · All rights reserved.