The IPC workhorse of the Eventide generation. The highest instruction-per-clock throughput of any core in the lineup — and the core that reintroduces Hyper-Threading to Intel's P-core class for the first time since Lion Cove removed it.
The Sunset Cove Dense Performance core takes the opposite architectural bet from the UHP Solar Eclipse. Where Solar Eclipse pursues frequency headroom at the expense of instruction-level depth, Sunset Cove maximizes IPC — instructions per clock cycle — across every execution unit in the design. It is the core in the Eventide lineup that extracts the most useful computation from every cycle that elapses, regardless of what that clock frequency is.
The headline numbers reflect this: +38% IPC over the Panther Lake P-core (Cougar Cove), which was itself a significant IPC improvement over its predecessors. At the same operating frequency, a Sunset Cove core completes 38% more work per cycle than the last-generation flagship. This is an architectural achievement that comes from three compounding decisions: the widest decode front-end on the chip, the deepest out-of-order execution window, and the most ambitious multi-porting strategy in recent x86 history.
The Sunset Cove is also the core that makes one of the most architecturally significant reversals in recent Intel history: the reintroduction of Hyper-Threading to the P-core class. Intel removed SMT from its Performance cores starting with Lion Cove in Lunar Lake, citing the latency and execution port contention problems that traditional SMT introduced. Sunset Cove re-adds it — but with a fundamentally re-engineered implementation that specifically addresses those prior criticisms.
Intel's original Hyper-Threading, as implemented through Alder Lake and prior generations, shared execution ports between the two hardware threads on each P-core. When both threads were running instructions that needed the same execution unit at the same time, one thread had to wait. The result was a technology that provided genuine multi-thread throughput in some workloads, but introduced latency unpredictability in others — particularly in latency-sensitive gaming scenarios where thread contention caused frame time variance. Lion Cove in Lunar Lake removed SMT entirely from P-cores for this reason. The simplification improved single-thread predictability and reduced power, and for Lunar Lake's efficiency-first mission, that was the right call.
Sunset Cove re-adds SMT, but with a different design: P-SMT uses disjoint execution port allocation. The two hardware threads on a Sunset Cove core do not share execution ports. Each thread is assigned a dedicated subset of the 20-port execution array. There is no runtime arbitration between threads for port access, no contention latency, and no head-of-line blocking. The result is SMT that genuinely behaves like having two narrower cores within one core's die footprint — the instruction throughput per mm² is exceptional, without the latency pathologies that got SMT removed in the first place.
The 20-port execution array is the physical implementation of the P-SMT promise. At 20 ports across a dual-thread design, each thread effectively has access to the equivalent of a 10-port out-of-order engine — which, for reference, is wider than the execution arrays of most prior-generation Intel P-cores. This is not a compromise configuration. This is a dual high-performance execution engine housed in a single core.
The 720-entry Reorder Buffer is the other key enabler. The ROB is the OOO window — it defines how many instructions ahead of the current commit point the processor can speculatively execute. A 720-entry ROB means the Sunset Cove can have 720 in-flight micro-operations at once across both hardware threads. This deep speculative window allows the core to continue finding work to do even when individual threads are waiting on memory accesses, branch misprediction recovery, or long-latency instructions. For multi-threaded workloads where both threads are executing non-trivially, this is where the +92% MT throughput figure comes from.
The 128 KB L0 extra-LLC is the largest on-chip L0 in the Eventide lineup — larger than the Solar Eclipse's 96 KB — because a 10-wide decode front-end serving two threads simultaneously has proportionally higher instruction fetch bandwidth requirements. The 6 MB private L2 is similarly the largest per-core L2 in the lineup, reflecting the working set pressure that two active threads generate.
The Sunset Cove carries the largest private cache of any core in the Eventide lineup. The 128 KB L0 extra-LLC, the 256 KB private L1, and the 6 MB private L2 are all sized for the bandwidth requirements of two active hardware threads simultaneously feeding a 10-wide decode front-end. L2 misses are absorbed first by the 12 MB Compute Tile shared L3 before reaching the photonic fabric.
The Sunset Cove core is the Hardware Thread Director's choice for workloads that are IPC-bound and multi-threaded simultaneously — scenarios where raw instruction throughput per core matters more than frequency headroom or core density. These are the workloads where the 720-entry ROB, 20-port disjoint execution array, and P-SMT combine into a result that no single-threaded or density-optimized core can match.