Per-shader power gating is the defining microarchitectural innovation of the Xe4E core — a technique borrowed from CPU design and applied to GPU execution units for the first time in a production graphics processor. In traditional GPU architectures, the entire shader array must be powered on whenever any workload is active; individual execution units cannot be selectively shut down based on demand. Xe4E breaks this constraint. Each EU (execution unit) within the Xe4E core has independent power-gate transistors that allow it to enter a deep sleep state within a single clock cycle, and wake within two cycles. The granularity is per-shader, not per-core — meaning that in a 14-core D390, the active shader count continuously adjusts to match the instantaneous workload, from a single EU to all 3,584.

Adaptive clock stepping complements per-shader gating with per-core frequency scaling at sub-millisecond granularity. Rather than operating at a single boost clock until thermal limits are hit, each Xe4E core independently selects from a 32-step frequency ladder based on real-time ALU utilization feedback. A core running at 15% occupancy drops to 800 MHz; the same core at 95% occupancy scales to 2.4 GHz — all within the same frame, with no driver intervention.

The result is a GPU that sustains a 3W active power floor for lightweight 3D workloads — UI compositing in light games, hardware video decode overlay, Windows animation effects — while scaling to 22W only when the workload genuinely demands it. The +58% performance-per-watt improvement over the prior Panther Lake Arc B390 is not achieved by clock speed or shader count increases, but by eliminating the wasted power that traditional GPU architectures burn on idle execution resources.

XMX4E is the dedicated AI matrix accelerator embedded within the Xe4E GPU architecture — purpose-built for the high-throughput, burst-mode AI workloads that demand GPU-class compute. Real-time image upscaling, AI-driven video enhancement, diffusion model inference, frame generation, and per-pixel super-resolution all require sustained matrix throughput that only a tightly coupled GPU accelerator can deliver. XMX4E provides that capability directly inside the LP GPU tile, eliminating the latency and bandwidth overhead of offloading to a discrete compute block.

Native support for INT4, INT8, FP8, and BF16 precision formats covers the full spectrum of modern inference models. INT4 quantized models — the dominant format for efficient edge AI in 2027 — run at peak efficiency on XMX4E, delivering ~553 TOPS at the D390’s 14-core configuration. This is not a theoretical peak calculated from matrix unit count; it is a sustained throughput figure measured under continuous inference load with thermal steady-state power consumption.

On fully configured Eventide APUs, AI workloads are segmented across four purpose-built engines. The LPNPU handles always-on ambient AI — lightweight neural networks that run continuously at near-zero power even with every other block powered down. The HNPU handles batch-mode and dedicated NPU inference: large model pipelines, XeSS acceleration, and sustained throughput workloads that leverage its 256 TOPS and 32 MB scratchpad. XMX4E fills the LP GPU tier — GPU-coupled inference that runs on the Druid tile alongside rendering and media decode, with direct access to on-die frame buffers. On configurations that pair Druid with an Elementalist iGPU, XMX5 operates in parallel as the high-throughput matrix engine — handling heavy diffusion, frame generation, and large-model inference at full GPU-class bandwidth. All four engines activate independently and can run simultaneously without contention.

RTU4 brings hardware-accelerated ray tracing to efficiency-class GPUs for the first time in Intel’s lineup. Previous LP iGPUs relied on shader-based (software) ray tracing, which consumed 5–10× the power of dedicated RT hardware for equivalent visual quality. RTU4’s fixed-function BVH traversal unit handles the computationally expensive acceleration structure traversal in dedicated silicon, freeing the Xe4E shader cores to focus exclusively on shading and lighting calculations.

The RTU4 design prioritizes quality-per-watt over raw throughput. It is not intended to compete with RTU5’s multi-level BVH4 traversal for heavy RT workloads — that is Xe5’s domain. Instead, RTU4 targets a specific class of ray tracing use cases: ambient occlusion, soft shadows, single-bounce reflections, and area-light sampling for indoor scenes. These are the RT effects that transform a game from “flat and game-like” to “believable” — and RTU4 can render them at mobile TDPs (10–15W) where software RT would be prohibitively expensive.

Area-light sampling is RTU4’s standout feature for visual quality-per-ray. Traditional point-light ray tracing requires many rays to approximate the soft shadow falloff of real-world area lights (windows, panels, lamps). RTU4 implements hardware-level area light importance sampling that produces equivalent shadow softness with 3–4× fewer rays per light, enabling realistic indoor lighting at the limited ray budgets appropriate for an efficiency-class GPU.

Intel 06E is not a derivative of Intel 04A — it is a purpose-designed efficiency process node developed in parallel. Where 04A optimizes for peak transistor performance (highest drive current, fastest switching speed, maximum frequency ceiling), 06E optimizes for the opposite end of the design space: minimum leakage current, lowest operating voltage, and smallest power-per-transistor at moderate frequencies. The Xe4E core, the UHE Lunar Eclipse CPU core, the LPNPU, and the LP Island’s supporting logic are all fabricated on 06E, forming Eventide’s always-on efficiency substrate.

The headline metric is −35% power per transistor compared to Intel 04A at equivalent logic density. This is achieved through a combination of high-threshold-voltage (high-Vt) transistor variants, longer gate lengths where timing closure permits, and Intel’s Adaptive Body Bias (ABB) technique that dynamically adjusts the transistor substrate voltage to minimize leakage during low-activity periods. At standby, the 06E die achieves leakage current below TSMC N5 — a node two full generations older — while delivering higher performance density when active.

The co-design between 06E and 04A is a critical but invisible aspect of Eventide’s architecture. Both nodes share the same metallization pitch in their upper interconnect layers, enabling the LP Island (06E) to bond directly to the Compute Tile (04A) through FOveros 2.0 without impedance-matching bridge logic. Data flows between the 04A and 06E dies at full fabric speed, with no protocol translation or bandwidth penalty — a level of cross-node integration that is only possible when both process nodes are designed within the same foundry ecosystem.