Arc Elementalist is Intel's Xe5 flagship GPU architecture. It scales as a single coherent render device — from one tile in a thin-and-light to four E1080 tiles in a 2,000 W workstation — joined over FOveros 2.0 photonic fabric and built on Intel 04A. 512-shader Xe5 cores with out-of-order wave dispatch and the XeAVX-2048 vector ISA. XMX5 matrix acceleration with native FP64. RTU5 hardware ray tracing. Across four tiles it delivers up to 20× the raster performance of the RTX 5090 and ~27× the ray tracing.
The Xe5 shader core is the widest, deepest execution unit Intel has ever built for graphics. Each Xe5-core contains 512 unified shaders — double the 256-shader Xe4E — organised into 32-wide wavefronts with out-of-order wave dispatch. The front-end decodes up to 4 instructions per clock per wavefront, feeding a 512-entry reorder buffer so waves execute non-sequentially by data readiness — a CPU-microarchitecture technique that lets a wave stalled on a cache miss yield to a wave with data ready, eliminating the pipeline bubbles that plague in-order GPU schedulers. Feeding those lanes is a new 16 KB private L0-data cache per core, straight into the 32-wide wavefront ports, backed by a 192 KB L1 (up from 128 KB) and the per-16-core-cluster L0 instruction cache.
Riding those same ALUs is XeAVX-2048 — a 2048-bit-wide vector ISA extension, distinct from the matrix-only XMX5, that spans the entire precision range in one unit. At the low end it packs FP8 / INT8 / FP16 at 2×/4× rate per lane for shadows, particles and post-process; at the high end it runs native FP64 at 1/2 FP32 rate, not emulated through FP32 pairs. That width is what makes the E1080's double-precision throughput workstation-real rather than a checkbox: the same silicon that shades a game frame runs HPC-class FP64 vector math, no discrete compute card required. Against the Xe2 generation in Battlemage, the Xe5 core retires 2.2× the instructions per clock.
Xe5 raster delivers ~5× per tile — 20× across four through five compounding engines: a tile-based binning rasterizer, Nanite-class virtualized geometry, predictive variable-rate shading, feedback-streamed textures, and a wide shader vector ISA. Each contributes a measured multiplier.
The Kachelraster Engine bins geometry into 64×64px tiles and culls overdraw before shading, against a 2 MB on-die bin buffer per raster cluster (shared with L2). Occluded fragments never reach the shader array — ~40% less overdraw and ~35% less bandwidth than immediate-mode rendering.
The Feingeometrie Engine clusters micro-triangles roughly 128 to a group for Nanite-class geometry virtualization, with the full cluster hierarchy resident on-package in Kache Kore's 4 GB bLLC. It shares PHR's residency mechanism with RT's BVH caching — one cache infrastructure, two consumers.
Each contributor is a measured multiplier, not a headline. They compound — and the product lands on the same ~4.8–5×/tile the platform already publishes, which becomes 20× across ×4 tiles.
The 2D Kanvas Renderer pulls UI, HUD and overlay compositing out of the 3D pipeline entirely. That is worth a real but small +3–5% effective 3D throughput — the 1.04× term above. It is listed as its own line precisely because it should not be folded into the larger multipliers to inflate them.
XMX5 makes a discrete AI accelerator unnecessary. Each unit delivers 2× the per-clock throughput of XMX4E at equal precision, and adds native INT2 and FP4 — sub-byte formats that quadruple effective throughput on quantized models. For XeSS 5.0 it generates whole intermediate frames from a temporal neural network at native resolution. A dedicated 512 KB L1 AI SRAM per cluster keeps model weights local, off the memory-bandwidth wall, and hardware sparse-activation skipping detects and bypasses zero-valued elements for up to 1.8× on the 40–60% sparsity real models carry.
RTU5 performs only ray–AABB and ray–triangle intersection — it never builds trees. It runs fourth-order bounding volume hierarchy (BVH4) traversal, four children per node instead of the industry-standard two, halving tree depth for the same scene, with hardware ReSTIR resampling hundreds of candidate light paths into converged global illumination on a fraction of a brute-force budget, and stereo BVH caching that re-traverses one structure for both eyes in VR. BVH construction, refit, pruning and residency run on dedicated silicon instead — the Symbiotic BVH Pipeline, the Kache Kore Prune Array, Persistent Hierarchy Residency and the Photonic Ray Mesh — keeping the intersection hardware at peak. Motion vectors, GI probe evaluation, contact shadows and multi-bounce proxy rays each run on a dedicated fixed-resolver, moving closed-form math out of shader code and into silicon.
| Single tile | ×4 tiles · Photonic Ray Mesh | |
|---|---|---|
| Raw hardware RTU5 silicon only · DXR 1.2 / Vulkan RT 1.4 |
4.2× | 16.8× |
| Effective + SBP / KPA / PHR eliminating build & refit overhead |
6.7× | ~27× |
BVH work splits into two problems with different latency profiles. The Symbiotic BVH Pipeline routes the tree-critical path and the bulk leaf refit to separate core classes. The Kache Kore Prune Array discards missing rays in-cache. Persistent Hierarchy Residency pins static geometry across frames. And the Photonic Ray Mesh lets four tiles trade ray and node work as one engine over the photonic fabric.
Per the Eventide family table, Core 500 has no Compute Tile, Core i500 has a Compute Tile but no SPE cores, and Core Ultra 500 carries only limited SPE. SBP Stage 2 is therefore not SPE-exclusive: on tiers without SPE it falls back to idle LPE (Darkmont) cores. Every tier runs the same SBP behavior — same two-stage split, same profile-aware routing — with less parallel throughput lower down the stack, never a different or absent feature. Stage 1's target likewise follows the active AFFINITY profile (DP under Performance/Unleashed, UHE under Balanced/Efficiency), an extension of Thread Director's existing profile-aware dispatch rather than a new mechanism.
The same design principle the platform already applies to fixed-function acoustic compute — closed-form geometric terms evaluated in dedicated silicon rather than shader code — applied here to graphics. Each resolver replaces a screen-space approximation or a redundant pass with an exact, near-free evaluation.
Elementalist addresses the platform's unified memory as VRAM. Six tiers — L0 through the Kache Kore L4 and out to terabyte-class ZAM — form one coherent hierarchy with no PCIe wall. The centerpiece is Kache Kore: a 4 GB bLLC (bandwidthLLC) fabricated on Intel 04A alongside the compute tiles. For the GPU, Kache Kore acts as an enormous L4 cache that absorbs the working set of most 1440p and many 4K game frames entirely on-package, eliminating the latency penalty of DRAM round-trips. Each Xe5 tile maintains its own L2 cache (12 MB/tile, 48 MB total across ×4 E1080) plus a new 24 MB tile-level L3 shared across the Xe5-core clusters, RTU5 and XMX5 — where the KPA pruning logic sits before a miss falls through to Kache Kore — with hardware cache coherency across tiles via FOveros 2.0. When a tile's L2 misses, the request hits Kache Kore at ~8 ns latency — comparable to dedicated GDDR7 on discrete GPUs — before falling through to Intel Z-Angle Memory (ZAM) mounted directly on the FOveros 2.0 photonic substrate. Unlike conventional DDR6/LPDDR6, ZAM is bandwidth and density-optimized for sustained high-throughput workloads, delivering 2–3 TB/s per controller and an effective 5–6 TB/s across both dual-channel ZAM controllers — dwarfing the bandwidth envelope of any discrete GDDR7 stack. Smart Memory Tiling automatically pins frequently-accessed texture mipmap levels and shader constants in Kache Kore, ensuring that bandwidth-critical data stays on-package.
Click a tier to see what it holds and why it was added. The prior hierarchy was L0-instruction only, 128 KB L1, 8 MB L2 and the Kache Kore L4 — with no L0-data and no tile-level L3.
The Xe5 GPU tiles are built on Intel 04A, the same node as the Eventide Compute Tile, and joined by FOveros 2.0 — a second-generation photonic interconnect that binds up to four GPU tiles into a single coherent device: one memory space, one command queue, over on-package silicon photonic waveguides. Unlike organic substrate interconnects that measure latency in nanoseconds and bandwidth in hundreds of GB/s, FOveros 2.0 uses on-package silicon photonic waveguides to deliver sub-2-nanosecond tile-to-tile latency at over 3.2 TB/s aggregate bisection bandwidth. The operating system and application see one GPU, one memory space, one command queue. Shader work distribution across tiles, cross-tile L2 cache coherency, and synchronized display output are all handled in hardware by the FOveros tile controller — with zero driver overhead. This is not SLI. This is not CrossFire. This is one GPU, built from four tiles, with single-GPU programming semantics.
The E1080 is the hero of its own chart: switch the metric, scale the tile count from ×1 to ×4, and watch it lead the field on a log axis that keeps every competitor visible instead of flattening them. Raw and effective RT figures stay labeled separately, exactly as on the RTU5 chart above, and any transitively-derived number carries its derivation on the number itself — never a footnote.
Bolt's Zeus is an offline rendering and simulation accelerator: a discrete card built to path-trace scenes and hold very large datasets, not to drive frames in real time. Elementalist is built for the frame — real-time hardware ray tracing, XeSS 5.0, and unified-tile raster for games and creation. Two different products for two different jobs, shown here on the same axes for reference.
On the two specifications Zeus markets hardest, the top Eventide platform holds the line: its unified memory reaches up to 4 TB (2 TB on-package ZAM plus up to 2 TB DDR6) against Zeus's 2.25 TB LPDDR5X, and XeAVX-2048 delivers native FP64 on the shader ALUs. On real-time ray tracing — the E1080's purpose — it leads decisively. Every Zeus figure below is Bolt's own published claim.
| Metric | RTX 5090 | RX 9070 XT | Bolt Zeus | Adreno X2-90 |
|---|---|---|---|---|
| Raster · vs E1080 ×4 | baseline → 20× | ~44× derived | not a raster-first part | not comparable tier |
| RT / path tracing · vs RTX 5090 | 1× (RT baseline) | ~0.45× derived | ~10× PT offline · claim | not comparable tier |
| E1080 ×4 RT vs part | 16.8× raw / ~27× eff | ~37× raw / ~59× eff derived | different workload (offline PT) | not comparable tier |
| FP32 compute | ~105 TFLOPS | mid-range tier | rendering/HPC-class · native FP64 | LP tier |
| Process node | TSMC 4N-class | TSMC N4 | TSMC (announced) | TSMC 3nm |
| Memory | 32 GB GDDR7 · ~1.8 TB/s | 16 GB GDDR6 | up to 2.25 TB LPDDR5X claim · below the X9 platform's up-to-4 TB unified ZAM+DDR6 | 228 GB/s LPDDR5X (SoC-shared) |
| Category | Real-time gaming flagship | No flagship-tier part this gen, by choice | Offline rendering / simulation accelerator (vendor claims) | SoC iGPU — TOPS/efficiency cross-reference only |