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AI Compute · HNPU · Intel 04A

256 TOPS. On the World's Most Advanced Node.

The HNPU is the primary AI compute engine for on-device LLM inference, Copilot+ compliance, real-time upscaling, and heavy background AI workloads. Manufactured on Intel 04A—the same cutting-edge node as the HPiGPU—the HNPU delivers unprecedented neural network density and power efficiency for next-generation client compute.

Intel 04A 256 TOPS INT2→FP32 OpenVINO 5.0 XeSS 5.0 Sole Intel IP
256
TOPS Peak Throughput
32
MB Scratchpad SRAM
7
Precision Modes
344
TOPS w/ LPNPU

Tile-Array NPU Architecture

The HNPU employs a distributed tile-array architecture optimized for sustained AI inference and model execution. Each tile operates as an independent compute island, enabling fine-grained parallelism across neural network operations without introducing latency penalties or synchronization bottlenecks.

INT2 matrix multiplication is the cornerstone of the HNPU's breakthrough throughput. By reducing datapath width to 2-bit integer operations, the HNPU achieves 4× the effective throughput of INT4 at the same silicon area—critical for quantized LLM inference where model weights occupy the vast majority of memory bandwidth. This precision mode unlocks aggressive model compression without sacrificing inference latency.

The 32 MB on-die scratchpad SRAM eliminates external memory round-trips for model weight staging and temporary activations, drastically reducing power consumption during inference. The scratchpad acts as a unified working memory for tile-to-tile data movement, enabling high-bandwidth, low-latency model execution.

The Hardware Thread Director coordinates task routing between HNPU and LPNPU, escalating background AI workloads upward only when power budget and thermal headroom permit sustained execution.

AI Throughput
256 TOPS (INT2); 180 TOPS (INT4); 64 TOPS (FP16)
Process Node
Intel 04A (CMOS)
Precision Modes
INT2, INT4, INT8, FP8, BF16, FP16, FP32
On-Die SRAM
32 MB Scratchpad (tile-to-tile coherency)
Supported Frameworks
OpenVINO 5.0, ONNX Runtime, TensorFlow Lite, PyTorch Export
Power Envelope
~6–8 W sustained; ~12–14 W turbo
Copilot+ Compliance
256 TOPS = 6.4× minimum 40 TOPS requirement

Precision Modes & Effective Throughput

INT2
256T
Quantized LLMs, aggressive compression
INT4
180T
Fine-tuned model weights, inference
INT8
120T
Activation quantization, int-only paths
FP8
96T
Lightweight float inference, AI sampling
BF16
48T
Mixed-precision training, bfloat16 models
FP16
48T
Float inference, backward compatibility
FP32
~12T
Research inference, high-precision paths

HNPU × XeSS 5.0 Pipeline

The HNPU seamlessly integrates with the Elementalist GPU's XeSS 5.0 upscaling engine, decoupling AI-driven temporal frame reconstruction from traditional rasterization latency. While the Elementalist handles pixel rasterization, the HNPU executes low-resolution neural networks for temporal motion estimation, feature synthesis, and perceptual enhancement.

Model inference runs entirely on the HNPU's tile array, freeing GPU XMX5 matrix units for parallel compute offloading. This co-execution model enables real-time upscaling at 4K+ resolutions without forcing games to choose between AI enhancements and maximum frame rate.

XeSS 5.0 is production-ready across AAA titles, with dedicated support in Unreal Engine 5.5 and a growing ecosystem of validated game publishers. The HNPU's INT2 quantization pipeline ensures model size stays under 64 MB, fitting entirely in tile SRAM for zero-copy execution.

XeSS 5.0 Support
Native neural upscaling pipeline, dedicated HNPU path
Frame Rate Impact
~0.5–1.2 ms per frame (independent of GPU load)
Model Footprint
~32–48 MB (INT2 quantized, on-die SRAM resident)
Target Resolutions
1440p → 4K, 1080p → 4K, 720p → 1440p native
API Integration
DirectX 12, Vulkan (with XeSS 5.0 extensions)
Engine Support
Unreal Engine 5.5+, custom pipelines via OpenVINO

Hardware Thread Director: Escalation Model

Level 1: LPNPU
Always-on, low-power background AI. Transcription, translation, ambient listening, telemetry inference. Power budget: ~0.3–0.5 W continuous.
→
Level 2: HNPU
Primary inference engine. LLM chat, Copilot+, XeSS upscaling, local AI agents. Activated by app demand or thermal headroom. Power budget: ~6–12 W sustained.
→
Level 3: GPU XMX5
Parallel matrix flood for large batch inference, training workloads, or collaborative tasks with CPU. Unrestricted power envelope; driven by OS scheduling.

Primary Use Cases

◆
On-Device LLM Inference
Host Copilot+, private AI assistants, and local language models directly on silicon. 256 TOPS enables real-time token generation for 7B–13B parameter models with full context windows.
◆
XeSS 5.0 Real-Time Upscaling
Neural frame upscaling for gaming. Temporal reconstruction runs on HNPU while Elementalist handles rasterization—zero render latency overhead.
◆
Background Diffusion & Generative AI
Image generation, video frame interpolation, and style transfer. HNPU offloads heavy lifting from CPU/GPU, enabling responsive UI and battery efficiency.
◆
Real-Time Transcription & Translation
Speech-to-text, live caption generation, and multilingual translation. HNPU enables enterprise-grade transcription without cloud round-trips.

Generation-on-Generation: vs Lunar Lake NPU 4.0

Peak Throughput
256T
Eventide HNPU vs Lunar Lake 120 TOPS: +112% uplift
Power Efficiency (perf/watt)
3×
Eventide HNPU: ~35 TOPS/W vs Lunar Lake ~12 TOPS/W