Intel Z-Angle Memory is a proprietary vertical-stack memory architecture purpose-built for bandwidth and density — Intel’s in-house answer to the AI memory revolution. Unlike HBM used in data-centre GPUs, ZAM is designed from the ground up for client APU workloads: mixed AI inference, GPU rendering, and latency-tolerant CPU access patterns operating simultaneously across a unified address space. The “Z-angle” name refers to the vertical interconnect topology: memory dies are stacked using through-silicon vias (TSVs) at optimised angles that minimise signal path length while maximising the number of parallel data channels per unit area — achieving bandwidth density that conventional planar DRAM cannot approach.

Each ZAM stack contains multiple DRAM dies connected via wide I/O interfaces, delivering 2–3 TB/s per controller — bandwidth that dwarfs DDR6 by an order of magnitude and exceeds discrete GDDR7 by roughly 3×. The chips mount directly on the FOveros 2.0 photonic substrate rather than through a traditional DIMM socket. This photonic-proximity mounting eliminates the electrical signalling losses of socketed memory, reduces parasitic capacitance, and enables the memory controller to drive the I/O links at maximum frequency without signal-integrity margin penalties. ZAM is bandwidth-optimised, not latency-optimised — raw access latency is approximately 40% higher than GDDR7. This is an intentional design trade-off: for AI inference, GPU texture streaming, and large working-set workloads, bandwidth is the bottleneck, not latency. The Kache Kore™ 4 GB bLLC at ~8 ns access time masks the latency for hot data, making the disadvantage invisible for the vast majority of access patterns. Power efficiency is exceptional: ZAM draws approximately 75% less power than an equivalent-bandwidth GDDR7 configuration because the short photonic-proximity signal paths require far less drive current. Inline ECC correction at Xeon 500 class ensures data integrity without bandwidth overhead.

The memory controller tile is the silicon brain of the Eventide memory subsystem, fabricated on Intel’s 14A-E efficiency process node. The base configuration includes two dual-channel ZAM controllers, each managing one ZAM memory stack and delivering 2–3 TB/s of bandwidth. The controllers operate independently but present a unified address space to all compute tiles — every CPU core, every Xe5 shader, every NPU engine sees the same flat memory map.

The controller tile connects to the ZAM stacks through the FOveros 2.0 photonic substrate, using silicon photonic waveguides rather than electrical traces. Memory requests travel at the speed of light through on-package optical interconnects with sub-nanosecond signalling overhead. Each controller implements hardware-level memory scheduling that prioritises requests based on source tile and workload class: GPU texture fetches get bandwidth priority; CPU cache-line fills get latency priority. The Hardware Thread Director’s workload classification feeds directly into the memory scheduler, ensuring that the right data moves to the right consumer at the right time. The controller manages power states per channel, allowing unused channels to enter deep sleep independently while active channels run at full bandwidth. Write-coalescing buffers aggregate small writes into full-width ZAM bursts, maximising bandwidth utilisation for scatter-write patterns common in GPU rendering and AI weight updates. The 14A-E process choice — rather than the 04A used for compute tiles — is deliberate: memory controllers are not frequency-bound workloads. 14A-E offers substantially lower leakage current and lower power per transistor, the right optimisation for silicon that runs continuously managing memory traffic.

Higher-SKU Eventide processors — Core Ultra 500 and Xeon 500 — add a third dual-channel memory controller supporting standard DDR6-9600+ or LPDDR6X-10400 memory, providing up to an additional 1 TB of conventional DRAM for a total unified capacity of 2 TB. This is not a replacement for ZAM — it is a complementary tier. DDR6 serves as the high-capacity expansion layer for datasets that exceed ZAM’s 1 TB ceiling, and as the staging buffer in the DirectStorage 2.0 pipeline where entire game worlds can be pre-loaded before streaming into ZAM at runtime.

DDR6-9600+ represents the fastest conventional memory standard, offering lower latency than ZAM but substantially lower bandwidth per channel. For latency-sensitive CPU workloads with small working sets that miss the bLLC, DDR6 provides better worst-case access times. LPDDR6X-10400 is the mobile variant, chosen for thinner form factors where DIMM slots are impractical — it offers 10,400 MT/s transfer rates with lower power draw than full DDR6. The third controller is fully unified into the same coherent address space as the ZAM controllers. The operating system and applications see a single, contiguous memory pool. The Hardware Thread Director and memory scheduler automatically place data on the optimal tier: hot working sets on Kache Kore™ bLLC, active runtime data on ZAM, large datasets and staging buffers on DDR6. Full ECC support ensures data integrity across the DDR6 tier as well.

The Eventide APU implements true unified memory: every byte of ZAM and DDR6 is accessible by every tile — CPU compute tile, GPU Xe5 tiles, GPU Xe4E tile, NPU (HNPU), 2DKR, and all ancillary tiles — through a single coherent address space. This is not the “unified memory” marketing of previous APUs where CPU and GPU technically shared DRAM but required explicit copy operations or driver-managed page migration. Eventide’s FOveros 2.0 photonic fabric implements hardware cache coherency across all tiles. When the CPU writes to an address, the GPU’s view of that address is automatically updated through the coherency protocol — no memcpy, no staging buffer, no driver intervention.

The elimination of CPU-to-GPU copies has profound implications for real-world workloads. In traditional discrete GPU architectures, transferring a 256 MB texture from system memory to GPU memory takes measurable time and consumes PCIe bandwidth. On Eventide, the texture is simply mapped into the unified address space. The GPU accesses it directly. If the texture is hot, it lives in Kache Kore. If it is warm, it lives in ZAM. If it is cold, it lives in DDR6. The memory scheduler handles tier placement transparently. For AI workloads, unified memory means the HNPU can access the same model weights the CPU prepared without any data movement. For gaming, DirectStorage-loaded assets can be accessed by the GPU the instant they arrive in memory, with zero copy overhead. Smart Memory Tiling automatically pins frequently-accessed texture mipmap levels and shader constants in Kache Kore, ensuring bandwidth-critical data stays on-package. The coherency protocol operates over FOveros 2.0’s photonic interconnect at sub-2 ns signalling latency, making coherency transactions effectively invisible to the execution pipeline.

Intel DirectStorage 2.0 is the vertically integrated data pipeline that eliminates every bottleneck between NVMe storage and the GPU framebuffer. The pipeline has four tiers: NVMe storage streams game assets at PCIe 6.0 speeds into DDR6 staging memory. The memory scheduler pre-fetches anticipated assets from DDR6 into ZAM runtime memory based on the application’s access patterns. The hottest working set — textures currently being rendered, shader constants in active use, physics simulation state — is pinned in the Kache Kore™ 4 GB bLLC at approximately 8 ns latency, comparable to dedicated GDDR7 on discrete GPUs.

What makes this “vertical integration” is that Intel controls every layer: the NVMe controller, the PCIe 6.0 PHY, the DDR6 memory controller, the ZAM controllers, the Kache Kore bLLC, and the GPU L2/L1 caches. Every handoff between tiers is optimised in hardware, with zero CPU staging overhead and zero driver-managed buffer copies. For gaming, this means world-level streaming with zero stutter: the entire game world can reside in DDR6 (up to 1 TB), with the active play area in ZAM, and the immediate frame requirements in Kache Kore. As the player moves through the world, data migrates automatically through the tiers. The Hardware Thread Director coordinates the pre-fetch engine, using workload classification to predict which data will be needed next and begin staging it before the GPU requests it. The result is the elimination of the “shader stall” — the visible hitch that occurs when a GPU shader needs data that has not yet arrived from storage. On Eventide, the multi-tier pipeline ensures that data is always staged at least one tier ahead of where it is needed.